1. Field
The present embodiment relates to display control circuits and display devices. For example, the embodiment relates to a display control circuit and a display device for exchanging, with a plurality of masters, attribute information defining conditions for displaying video on a display.
2. Description of the Related Art
Methods have been conventionally known whereby attribute information or the like of a video display device (e.g., PC monitor or DTV) is exchanged between the video display device and a plurality of video output devices (e.g., DVD player, graphics card, etc.) via a DDC (Display Data Channel (I2C bus)) at their interface.
For example, when an identical slave (device addressed by masters) is accessed by multiple I2C single masters (devices that initiate data transfer, generate a clock signal, and terminate the data transfer), mastership over the bus is arbitrated (only one master is permitted to control the bus) in accordance with the connection configurations of the masters, to determine a master that is allowed to access the slave.
Generally, a video display device is equipped with a plurality of different video input connectors (HDMI (High-Definition Multimedia Interface), DVI (Digital Visual Interface), VGA (Video Graphics Array), etc.). Thus, to enable video output devices to acquire the attribute information on the video display device regardless of the connector type, the interfaces are defined by the Vesa DDC standard and the data contents are defined by EDID (Extended Display Identification Data), CEA (Consumer Electronics Association) 861, and HDMI.
However, since some of these standards do not allow for multi-master configuration, video display devices need to be designed taking account of a situation where masters with no arbitration function are connected.
FIG. 29 shows an exemplary configuration of a conventional display control circuit.
Where a display control circuit 90 is equipped with three channels of HDMI connectors 90a to 90c and one channel of DVI connector 90d, as shown in FIG. 29, it is necessary to provide the circuit with four nonvolatile memories 91a to 91d storing almost the same data (attribute information; in practice, only the port number and the checksum may differ), making the circuit configuration redundant.
As a configuration for avoiding the inconvenience, a technique has been known wherein multiple I2C single masters are made to access a single slave via a CPU (see, e.g., Unexamined Japanese Patent Publication No. 2006-126829).
The use of a CPU, on the one hand, makes it possible to reduce the number of memories but, on the other hand, leads to complexity of circuitry and also gives rise to a problem that costs cannot be substantially cut down.